31 #define QQQdialect MPLABX 45 #undef QQQMULTIPROCESSEXH 48 #define qqqMaxBranchDepth 20 49 #define QQQstructbitmap 61 #undef QQQTEMPLATEONLY 63 #define QQQUPLOADATEND 65 #undef QQQASHLINGVITRA 67 #define qqqbitmapint unsigned int 69 #undef QQQTIC2XSERIALIO 71 #undef QQQCOMPRESSED_EXH 78 #define switches_57zzopen zzopen 80 #define switches_57zqqzqz1 zqqzqz1 83 #define FILEPOINT FILE * f, 84 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 100 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 101 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 104 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 105 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 113 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 114 #ifndef LDRA_VOID_FUNC 115 #define LDRA_VOID_FUNC 118 #if defined(QQQMAINFL) 141 #ifdef QQQ_KEEPCOMMENTS 149 #if !defined(QQQSUPPRESS_UNDEF) 155 #undef QQQHITMAP_STORAGE 157 #define qqnull_params void 158 #define QQQ_PROTOTYPE_DEF 160 #undef QQ_ANSI_PROTOTYPE 162 #define QQ_ANSI_PROTOTYPE 1 165 #define QQ_ANSI_PROTOTYPE 1 171 #define ELEMENT(N) qqqbitmapint element##N; 173 #include "switches_57zbelem.def" 177 #define ELEMENT(N) 0, 179 #include "switches_57zbelem.def" 226 #define S3_NUM_OF_POSITIONS 5U 227 #define S6_NUM_OF_POSITIONS 3U 228 #define S4_NUM_OF_POSITIONS 2U 229 #define S1_NUM_OF_POSITIONS 2U 269 uint8_t knob_switch_S3 [ 5 ] ;
270 uint8_t key_switch_S6 [ 3 ] ;
271 uint8_t pol_switch_S4 [ 2 ] ;
272 uint8_t dump_fire_switch_S7 ;
273 uint8_t fire_switch_S1 [ 2 ] ;
274 uint8_t hvps_switch_S5 ;
279 uint16_t store_buffer [ 2 ] ;
281 uint8_t dump_fire_count ;
595 #ifndef _SYS_DEFINITIONS_H 596 #define _SYS_DEFINITIONS_H 605 #include "system/common/sys_common.h" 606 #include "system/common/sys_module.h" 690 #ifndef _SYSTEM_CONFIG_H 691 #define _SYSTEM_CONFIG_H 710 #define SYS_VERSION_STR "2.06" 711 #define SYS_VERSION 20600 715 #define SYS_CLK_FREQ 200000000ul 716 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 717 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 718 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 719 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 720 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 721 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 722 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 723 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 724 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 726 #define SYS_PORT_A_ANSEL 0x3F00 727 #define SYS_PORT_A_TRIS 0xFFED 728 #define SYS_PORT_A_LAT 0x0010 729 #define SYS_PORT_A_ODC 0x0000 730 #define SYS_PORT_A_CNPU 0x0020 731 #define SYS_PORT_A_CNPD 0x0000 732 #define SYS_PORT_A_CNEN 0x0021 733 #define SYS_PORT_B_ANSEL 0x10C8 734 #define SYS_PORT_B_TRIS 0x91FF 735 #define SYS_PORT_B_LAT 0x0000 736 #define SYS_PORT_B_ODC 0x0000 737 #define SYS_PORT_B_CNPU 0x0000 738 #define SYS_PORT_B_CNPD 0x0000 739 #define SYS_PORT_B_CNEN 0x0000 740 #define SYS_PORT_C_ANSEL 0xCFE1 741 #define SYS_PORT_C_TRIS 0xFFFF 742 #define SYS_PORT_C_LAT 0x0000 743 #define SYS_PORT_C_ODC 0x0000 744 #define SYS_PORT_C_CNPU 0x0000 745 #define SYS_PORT_C_CNPD 0x0000 746 #define SYS_PORT_C_CNEN 0x0000 747 #define SYS_PORT_D_ANSEL 0xC100 748 #define SYS_PORT_D_TRIS 0xFFFF 749 #define SYS_PORT_D_LAT 0x0000 750 #define SYS_PORT_D_ODC 0x0000 751 #define SYS_PORT_D_CNPU 0x0000 752 #define SYS_PORT_D_CNPD 0x0000 753 #define SYS_PORT_D_CNEN 0x0000 754 #define SYS_PORT_E_ANSEL 0xFC00 755 #define SYS_PORT_E_TRIS 0xFDFF 756 #define SYS_PORT_E_LAT 0x0000 757 #define SYS_PORT_E_ODC 0x0000 758 #define SYS_PORT_E_CNPU 0x0000 759 #define SYS_PORT_E_CNPD 0x0000 760 #define SYS_PORT_E_CNEN 0x0000 761 #define SYS_PORT_F_ANSEL 0xCEC0 762 #define SYS_PORT_F_TRIS 0xEFFF 763 #define SYS_PORT_F_LAT 0x0000 764 #define SYS_PORT_F_ODC 0x0000 765 #define SYS_PORT_F_CNPU 0x0000 766 #define SYS_PORT_F_CNPD 0x0000 767 #define SYS_PORT_F_CNEN 0x0000 768 #define SYS_PORT_G_ANSEL 0x8CBC 769 #define SYS_PORT_G_TRIS 0xDFFF 770 #define SYS_PORT_G_LAT 0x0000 771 #define SYS_PORT_G_ODC 0x0000 772 #define SYS_PORT_G_CNPU 0x0000 773 #define SYS_PORT_G_CNPD 0x0000 774 #define SYS_PORT_G_CNEN 0x0000 775 #define SYS_PORT_H_ANSEL 0x0070 776 #define SYS_PORT_H_TRIS 0xB3FB 777 #define SYS_PORT_H_LAT 0x0000 778 #define SYS_PORT_H_ODC 0x0000 779 #define SYS_PORT_H_CNPU 0x0000 780 #define SYS_PORT_H_CNPD 0x0000 781 #define SYS_PORT_H_CNEN 0x0000 782 #define SYS_PORT_J_ANSEL 0x0000 783 #define SYS_PORT_J_TRIS 0x8B7F 784 #define SYS_PORT_J_LAT 0x0080 785 #define SYS_PORT_J_ODC 0x0000 786 #define SYS_PORT_J_CNPU 0x0000 787 #define SYS_PORT_J_CNPD 0x0000 788 #define SYS_PORT_J_CNEN 0x0800 789 #define SYS_PORT_K_ANSEL 0xFF00 790 #define SYS_PORT_K_TRIS 0xFFFF 791 #define SYS_PORT_K_LAT 0x0000 792 #define SYS_PORT_K_ODC 0x0000 793 #define SYS_PORT_K_CNPU 0x0000 794 #define SYS_PORT_K_CNPD 0x0000 795 #define SYS_PORT_K_CNEN 0x0000 799 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 800 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 801 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 802 #define SYS_TMR_FREQUENCY 1000 803 #define SYS_TMR_FREQUENCY_TOLERANCE 10 804 #define SYS_TMR_UNIT_RESOLUTION 10000 805 #define SYS_TMR_CLIENT_TOLERANCE 10 806 #define SYS_TMR_INTERRUPT_NOTIFICATION false 812 #define DRV_IC_DRIVER_MODE_STATIC 815 #define DRV_SPI_NUMBER_OF_MODULES 6 818 #define DRV_SPI_POLLED 1 819 #define DRV_SPI_ISR 0 820 #define DRV_SPI_MASTER 1 821 #define DRV_SPI_SLAVE 0 823 #define DRV_SPI_EBM 1 824 #define DRV_SPI_8BIT 1 825 #define DRV_SPI_16BIT 1 826 #define DRV_SPI_32BIT 0 827 #define DRV_SPI_DMA 0 829 #define DRV_SPI_INSTANCES_NUMBER 3 830 #define DRV_SPI_CLIENTS_NUMBER 3 831 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 833 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 834 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 835 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 836 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 837 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 838 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 839 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 840 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 841 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 842 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 843 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 844 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 845 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 846 #define DRV_SPI_BAUD_RATE_IDX0 1000000 847 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 848 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 849 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 850 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 851 #define DRV_SPI_QUEUE_SIZE_IDX0 10 852 #define DRV_SPI_RESERVED_JOB_IDX0 1 854 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 855 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 856 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 857 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 858 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 859 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 860 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 861 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 862 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 863 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 864 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 865 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 866 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 867 #define DRV_SPI_BAUD_RATE_IDX1 1000000 868 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 869 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 870 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 871 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 872 #define DRV_SPI_QUEUE_SIZE_IDX1 10 873 #define DRV_SPI_RESERVED_JOB_IDX1 1 875 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 876 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 877 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 878 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 879 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 880 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 881 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 882 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 883 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 884 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 885 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 886 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 887 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 888 #define DRV_SPI_BAUD_RATE_IDX2 500000 889 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 890 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 891 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 892 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 893 #define DRV_SPI_QUEUE_SIZE_IDX2 10 894 #define DRV_SPI_RESERVED_JOB_IDX2 1 896 #define DRV_TMR_INTERRUPT_MODE true 898 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 899 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 900 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 901 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 902 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 903 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 904 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 905 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 906 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 907 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 908 #define DRV_TMR_POWER_STATE_IDX0 909 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 910 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 911 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 912 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 913 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 914 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 915 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 916 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 917 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 918 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 919 #define DRV_TMR_POWER_STATE_IDX1 921 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 922 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 923 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 924 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 925 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 926 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 927 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 928 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 929 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 930 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 931 #define DRV_TMR_POWER_STATE_IDX2 933 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 934 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 935 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 936 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 937 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 938 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 939 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 940 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 941 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 942 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 943 #define DRV_TMR_POWER_STATE_IDX3 945 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 946 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 947 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 948 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 949 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 950 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 951 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 952 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 953 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 954 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 955 #define DRV_TMR_POWER_STATE_IDX4 959 #define DRV_USART_INSTANCES_NUMBER 1 960 #define DRV_USART_CLIENTS_NUMBER 1 961 #define DRV_USART_INTERRUPT_MODE false 962 #define DRV_USART_BYTE_MODEL_SUPPORT true 963 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 964 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 972 #define DRV_USBHS_DEVICE_SUPPORT true 974 #define DRV_USBHS_HOST_SUPPORT false 976 #define DRV_USBHS_INSTANCES_NUMBER 1 978 #define DRV_USBHS_INTERRUPT_MODE true 980 #define DRV_USBHS_ENDPOINTS_NUMBER 2 983 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 985 #define USB_DEVICE_INSTANCES_NUMBER 1 987 #define USB_DEVICE_EP0_BUFFER_SIZE 64 989 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 997 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 998 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 999 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 1000 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 1001 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 1003 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1004 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1005 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1006 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1007 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 1009 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1010 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1011 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1012 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1013 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 1015 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1016 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1017 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1018 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1019 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 1021 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1022 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1023 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1024 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1025 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 1027 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1028 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1029 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1030 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1031 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 1033 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1034 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1035 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1036 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1037 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 1039 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1040 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1041 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1042 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1043 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 1045 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1046 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1047 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1048 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1049 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 1051 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1052 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1053 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1054 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1055 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 1057 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1058 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1059 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1060 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1061 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 1063 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1064 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1065 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1066 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1067 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 1069 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1070 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1071 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1072 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1073 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 1075 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1076 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1077 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1078 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1079 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 1081 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1082 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1083 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1084 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1085 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 1087 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1088 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1089 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1090 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1091 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 1093 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1094 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1095 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1096 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1097 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 1099 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1100 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1101 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1102 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1103 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 1105 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1106 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1107 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1108 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1109 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 1111 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 1113 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 1115 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 1117 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 1119 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 1121 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 1123 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 1125 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 1127 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 1129 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 1131 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 1133 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 1135 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 1137 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 1139 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 1141 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 1143 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 1144 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 1145 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 1146 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 1147 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 1148 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 1149 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 1198 #ifndef _DRV_COMMON_H 1199 #define _DRV_COMMON_H 1301 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 1311 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 1321 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1377 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1388 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1403 #define _PLIB_UNSUPPORTED 1411 #include "system/common/sys_module.h" 1423 #define DRV_IC_INDEX_0 0 1424 #define DRV_IC_INDEX_1 1 1425 #define DRV_IC_INDEX_2 2 1426 #define DRV_IC_INDEX_3 3 1427 #define DRV_IC_INDEX_4 4 1428 #define DRV_IC_INDEX_5 5 1429 #define DRV_IC_INDEX_6 6 1430 #define DRV_IC_INDEX_7 7 1431 #define DRV_IC_INDEX_8 8 1432 #define DRV_IC_INDEX_9 9 1433 #define DRV_IC_INDEX_10 10 1434 #define DRV_IC_INDEX_11 11 1435 #define DRV_IC_INDEX_12 12 1436 #define DRV_IC_INDEX_13 13 1437 #define DRV_IC_INDEX_14 14 1438 #define DRV_IC_INDEX_15 15 1470 const SYS_MODULE_INDEX index ,
1471 const SYS_MODULE_INIT *
const init ) ;
1493 const SYS_MODULE_INDEX drvIndex ,
1538 const SYS_MODULE_INDEX drvIndex ,
1671 #ifndef _DRV_IC_STATIC_H 1672 #define _DRV_IC_STATIC_H 1673 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1674 #define DRV_IC_Close( handle ) 1713 #include "system/devcon/sys_devcon.h" 1714 #include "system/clk/sys_clk.h" 1715 #include "system/int/sys_int.h" 1716 #include "system/tmr/sys_tmr.h" 1758 #ifndef _DRV_ADC_STATIC_H 1759 #define _DRV_ADC_STATIC_H 1760 #include <stdbool.h> 1761 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1762 #include "peripheral/adchs/plib_adchs.h" 1763 #include "peripheral/int/plib_int.h" 1803 uint8_t bufIndex ) ;
1807 uint8_t bufIndex ) ;
1857 #ifndef _DRV_TMR_STATIC_H 1858 #define _DRV_TMR_STATIC_H 1907 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1908 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1909 #include "peripheral/tmr/plib_tmr.h" 1945 #ifndef _TMR_DEFINITIONS_PIC32M_H 1946 #define _TMR_DEFINITIONS_PIC32M_H 2004 #include "system/int/sys_int.h" 2005 #include "system/clk/sys_clk.h" 2024 #define DRV_TMR_INDEX_0 0 2025 #define DRV_TMR_INDEX_1 1 2026 #define DRV_TMR_INDEX_2 2 2027 #define DRV_TMR_INDEX_3 3 2028 #define DRV_TMR_INDEX_4 4 2029 #define DRV_TMR_INDEX_5 5 2030 #define DRV_TMR_INDEX_6 6 2031 #define DRV_TMR_INDEX_7 7 2032 #define DRV_TMR_INDEX_8 8 2033 #define DRV_TMR_INDEX_9 9 2034 #define DRV_TMR_INDEX_10 10 2035 #define DRV_TMR_INDEX_11 11 2046 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 2131 uint32_t dividerMin ;
2133 uint32_t dividerMax ;
2136 uint32_t dividerStep ;
2152 SYS_MODULE_INIT moduleInit ;
2154 TMR_MODULE_ID tmrId ;
2158 TMR_PRESCALE prescale ;
2162 INT_SOURCE interruptSource ;
2170 bool asyncWriteEnable ;
2185 uint32_t alarmCount ) ;
2247 const SYS_MODULE_INDEX drvIndex ,
2248 const SYS_MODULE_INIT *
const init ) ;
2288 SYS_MODULE_OBJ
object ) ;
2335 SYS_MODULE_OBJ
object ) ;
2369 SYS_MODULE_OBJ
object ) ;
2423 const SYS_MODULE_INDEX index ,
2524 uint32_t counterPeriod ) ;
3014 TMR_PRESCALE preScale ) ;
3254 #ifndef _DRV_TMR_DEPRECATED_H 3255 #define _DRV_TMR_DEPRECATED_H 3296 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3360 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3425 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3484 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3545 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3604 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3665 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3695 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3727 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3758 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3790 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3852 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3917 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3934 #include "peripheral/tmr/plib_tmr.h" 3935 #include "peripheral/int/plib_int.h" 3937 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3939 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3941 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3943 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3962 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3968 static inline SYS_STATUS
3971 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3982 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3993 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
4003 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
4012 TMR_PRESCALE prescale ) ;
4043 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
4072 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
4078 static inline SYS_STATUS
4081 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
4092 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
4103 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
4113 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
4122 TMR_PRESCALE prescale ) ;
4153 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
4182 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
4188 static inline SYS_STATUS
4191 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
4202 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
4213 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
4223 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
4232 TMR_PRESCALE prescale ) ;
4263 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
4292 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
4298 static inline SYS_STATUS
4301 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
4312 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
4323 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
4333 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
4342 TMR_PRESCALE prescale ) ;
4373 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4402 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4408 static inline SYS_STATUS
4411 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4422 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4433 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4443 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4452 TMR_PRESCALE prescale ) ;
4483 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4502 #include "peripheral/int/plib_int.h" 4544 #ifndef _DRV_PMP_STATIC_H 4545 #define _DRV_PMP_STATIC_H 4546 #include "peripheral/pmp/plib_pmp.h" 4561 PMP_DATA_WAIT_STATES dataWait ,
4562 PMP_STROBE_WAIT_STATES strobeWait ,
4563 PMP_DATA_HOLD_STATES dataHold ) ;
4618 #ifndef _DRV_USART_STATIC_H 4619 #define _DRV_USART_STATIC_H 4658 #ifndef _DRV_USART_STATIC_LOCAL_H 4659 #define _DRV_USART_STATIC_LOCAL_H 4666 #include <stdbool.h> 4703 #ifndef _DRV_USART_H 4704 #define _DRV_USART_H 4744 #ifndef _DRV_USART_DEFINITIONS_H 4745 #define _DRV_USART_DEFINITIONS_H 4751 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4752 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4789 #ifndef _PLIB_USART_H 4790 #define _PLIB_USART_H 4833 #ifndef _USART_PROCESSOR_H 4834 #define _USART_PROCESSOR_H 4843 #include <stdbool.h> 4844 #error "No Processor Family specified" 4888 USART_MODULE_ID index ) ;
4918 USART_MODULE_ID index ) ;
4950 USART_MODULE_ID index ) ;
4984 USART_MODULE_ID index ,
4985 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
5014 USART_BRG_CLOCK_SOURCE
5016 USART_MODULE_ID index ) ;
5070 USART_MODULE_ID index ) ;
5100 USART_MODULE_ID index ) ;
5129 USART_MODULE_ID index ) ;
5161 USART_MODULE_ID index ) ;
5192 USART_MODULE_ID index ) ;
5234 USART_MODULE_ID index ) ;
5267 USART_MODULE_ID index ) ;
5299 USART_MODULE_ID index ) ;
5340 USART_MODULE_ID index ,
5341 uint32_t clockFrequency ,
5342 uint32_t baudRate ) ;
5383 USART_MODULE_ID index ,
5384 uint32_t clockFrequency ,
5385 uint32_t baudRate ) ;
5418 USART_MODULE_ID index ,
5419 int32_t clockFrequency ) ;
5454 USART_MODULE_ID index ,
5489 USART_MODULE_ID index ) ;
5524 USART_MODULE_ID index ,
5559 USART_MODULE_ID index ) ;
5591 USART_MODULE_ID index ) ;
5625 USART_MODULE_ID index ) ;
5658 USART_MODULE_ID index ) ;
5691 USART_MODULE_ID index ) ;
5725 USART_MODULE_ID index ,
5770 USART_MODULE_ID index ) ;
5804 USART_MODULE_ID index ) ;
5840 USART_MODULE_ID index ) ;
5877 USART_MODULE_ID index ,
5917 USART_MODULE_ID index ) ;
5955 USART_MODULE_ID index ) ;
5990 USART_MODULE_ID index ) ;
6024 USART_MODULE_ID index ) ;
6058 USART_MODULE_ID index ) ;
6091 USART_MODULE_ID index ) ;
6123 USART_MODULE_ID index ) ;
6155 USART_MODULE_ID index ) ;
6188 USART_MODULE_ID index ) ;
6222 USART_MODULE_ID index ) ;
6251 USART_MODULE_ID index ) ;
6280 USART_MODULE_ID index ) ;
6312 USART_MODULE_ID index ) ;
6344 USART_MODULE_ID index ) ;
6374 USART_MODULE_ID index ) ;
6404 USART_MODULE_ID index ) ;
6433 USART_MODULE_ID index ) ;
6462 USART_MODULE_ID index ) ;
6496 USART_MODULE_ID index ,
6497 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6529 USART_MODULE_ID index ,
6530 USART_RECEIVE_INTR_MODE interruptMode ) ;
6563 USART_MODULE_ID index ,
6564 USART_LINECONTROL_MODE dataFlowConfig ) ;
6597 USART_MODULE_ID index ,
6598 USART_HANDSHAKE_MODE handshakeConfig ) ;
6631 USART_MODULE_ID index ,
6662 USART_MODULE_ID index ) ;
6691 USART_MODULE_ID index ) ;
6722 USART_MODULE_ID index ) ;
6753 USART_MODULE_ID index ) ;
6783 USART_MODULE_ID index ) ;
6815 USART_MODULE_ID index ,
6816 USART_OPERATION_MODE operationmode ) ;
6846 USART_MODULE_ID index ) ;
6879 USART_MODULE_ID index ) ;
6908 USART_MODULE_ID index ) ;
6938 USART_MODULE_ID index ) ;
6974 USART_MODULE_ID index ) ;
7025 USART_MODULE_ID index ,
7028 bool wakeFromSleep ,
7073 USART_MODULE_ID index ,
7074 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
7075 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
7076 USART_OPERATION_MODE operationMode ) ;
7122 USART_MODULE_ID index ,
7123 uint32_t systemClock ,
7169 USART_MODULE_ID index ) ;
7190 USART_MODULE_ID index ) ;
7211 USART_MODULE_ID index ) ;
7245 USART_MODULE_ID index ) ;
7272 USART_MODULE_ID index ) ;
7298 USART_MODULE_ID index ) ;
7325 USART_MODULE_ID index ) ;
7351 USART_MODULE_ID index ) ;
7376 USART_MODULE_ID index ) ;
7402 USART_MODULE_ID index ) ;
7427 USART_MODULE_ID index ) ;
7453 USART_MODULE_ID index ) ;
7478 USART_MODULE_ID index ) ;
7504 USART_MODULE_ID index ) ;
7531 USART_MODULE_ID index ) ;
7557 USART_MODULE_ID index ) ;
7583 USART_MODULE_ID index ) ;
7610 USART_MODULE_ID index ) ;
7637 USART_MODULE_ID index ) ;
7664 USART_MODULE_ID index ) ;
7690 USART_MODULE_ID index ) ;
7715 USART_MODULE_ID index ) ;
7741 USART_MODULE_ID index ) ;
7768 USART_MODULE_ID index ) ;
7794 USART_MODULE_ID index ) ;
7820 USART_MODULE_ID index ) ;
7845 USART_MODULE_ID index ) ;
7870 USART_MODULE_ID index ) ;
7895 USART_MODULE_ID index ) ;
7921 USART_MODULE_ID index ) ;
7946 USART_MODULE_ID index ) ;
7972 USART_MODULE_ID index ) ;
7998 USART_MODULE_ID index ) ;
8023 USART_MODULE_ID index ) ;
8049 USART_MODULE_ID index ) ;
8074 USART_MODULE_ID index ) ;
8099 USART_MODULE_ID index ) ;
8126 USART_MODULE_ID index ) ;
8151 USART_MODULE_ID index ) ;
8177 USART_MODULE_ID index ) ;
8242 #include "system/common/sys_common.h" 8243 #include "system/common/sys_module.h" 8255 #include "system/int/sys_int.h" 8327 #ifndef _SYS_DMA_DEFINITIONS_H 8328 #define _SYS_DMA_DEFINITIONS_H 8334 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 8335 #include "system/common/sys_common.h" 8336 #include "system/common/sys_module.h" 8406 #ifndef _PLIB_DMA_PROCESSOR_H 8407 #define _PLIB_DMA_PROCESSOR_H 8408 #error "Can't find header" 8452 DMA_MODULE_ID index ,
8453 DMA_CHANNEL channel ) ;
8487 DMA_MODULE_ID index ,
8488 DMA_CHANNEL channel ,
8489 DMA_CHANNEL_COLLISION collisonType ) ;
8521 DMA_MODULE_ID index ,
8522 DMA_CHANNEL channel ) ;
8554 DMA_MODULE_ID index ,
8555 DMA_CHANNEL channel ) ;
8593 DMA_MODULE_ID index ,
8594 DMA_CHANNEL channel ,
8595 DMA_CHANNEL_PRIORITY channelPriority ) ;
8624 DMA_CHANNEL_PRIORITY
8626 DMA_MODULE_ID index ,
8627 DMA_CHANNEL channel ) ;
8655 DMA_MODULE_ID index ,
8656 DMA_CHANNEL_PRIORITY channelPriority ) ;
8681 DMA_CHANNEL_PRIORITY
8683 DMA_MODULE_ID index ) ;
8713 DMA_MODULE_ID index ,
8714 DMA_CHANNEL channel ) ;
8745 DMA_MODULE_ID index ,
8746 DMA_CHANNEL channel ) ;
8775 DMA_MODULE_ID index ,
8776 DMA_CHANNEL channel ) ;
8805 DMA_MODULE_ID index ,
8806 DMA_CHANNEL channel ) ;
8837 DMA_MODULE_ID index ,
8838 DMA_CHANNEL channel ) ;
8867 DMA_MODULE_ID index ,
8868 DMA_CHANNEL channel ) ;
8899 DMA_MODULE_ID index ,
8900 DMA_CHANNEL channel ) ;
8931 DMA_MODULE_ID index ,
8932 DMA_CHANNEL channel ) ;
8961 DMA_MODULE_ID index ,
8962 DMA_CHANNEL channel ) ;
8993 DMA_MODULE_ID index ,
8994 DMA_CHANNEL channel ) ;
9023 DMA_MODULE_ID index ,
9024 DMA_CHANNEL channel ) ;
9054 DMA_MODULE_ID index ,
9055 DMA_CHANNEL channel ) ;
9085 DMA_MODULE_ID index ,
9086 DMA_CHANNEL channel ) ;
9116 DMA_MODULE_ID index ,
9117 DMA_CHANNEL channel ) ;
9147 DMA_MODULE_ID index ,
9148 DMA_CHANNEL channel ) ;
9179 DMA_MODULE_ID index ,
9180 DMA_CHANNEL channel ) ;
9211 DMA_MODULE_ID index ,
9212 DMA_CHANNEL channel ,
9213 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
9242 DMA_CHANNEL_TRANSFER_DIRECTION
9244 DMA_MODULE_ID index ,
9245 DMA_CHANNEL channel ) ;
9281 DMA_MODULE_ID index ,
9282 DMA_CHANNEL channel ,
9284 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9317 DMA_MODULE_ID index ,
9318 DMA_CHANNEL channel ,
9319 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9350 DMA_MODULE_ID index ,
9351 DMA_CHANNEL channel ,
9352 uint16_t peripheraladdress ) ;
9380 DMA_MODULE_ID index ,
9381 DMA_CHANNEL channel ) ;
9412 DMA_MODULE_ID index ,
9413 DMA_CHANNEL channel ,
9414 uint16_t transferCount ) ;
9442 DMA_MODULE_ID index ,
9443 DMA_CHANNEL channel ) ;
9476 DMA_MODULE_ID index ,
9477 DMA_CHANNEL channel ,
9478 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9506 DMA_SOURCE_ADDRESSING_MODE
9508 DMA_MODULE_ID index ,
9509 DMA_CHANNEL channel ) ;
9542 DMA_MODULE_ID index ,
9543 DMA_CHANNEL channel ,
9544 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9573 DMA_DESTINATION_ADDRESSING_MODE
9575 DMA_MODULE_ID index ,
9576 DMA_CHANNEL channel ) ;
9609 DMA_MODULE_ID index ,
9610 DMA_CHANNEL channel ,
9611 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9639 DMA_CHANNEL_ADDRESSING_MODE
9641 DMA_MODULE_ID index ,
9642 DMA_CHANNEL channel ) ;
9680 DMA_MODULE_ID index ,
9681 DMA_CHANNEL channel ,
9682 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9718 DMA_MODULE_ID index ,
9719 DMA_CHANNEL channel ,
9720 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9755 DMA_MODULE_ID index ,
9756 DMA_CHANNEL channel ,
9757 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9786 DMA_CHANNEL_INT_SOURCE
9788 DMA_MODULE_ID index ,
9789 DMA_CHANNEL channel ) ;
9824 DMA_MODULE_ID index ,
9825 DMA_CHANNEL channel ,
9826 DMA_TRIGGER_SOURCE IRQnum ) ;
9861 DMA_MODULE_ID index ,
9862 DMA_CHANNEL channel ,
9863 DMA_TRIGGER_SOURCE IRQ ) ;
9894 DMA_MODULE_ID index ,
9895 DMA_CHANNEL channel ,
9896 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9923 DMA_CHANNEL_DATA_SIZE
9925 DMA_MODULE_ID index ,
9926 DMA_CHANNEL channel ) ;
9960 DMA_MODULE_ID index ,
9961 DMA_CHANNEL channel ,
9962 DMA_TRANSFER_MODE channeltransferMode ) ;
9994 DMA_MODULE_ID index ,
9995 DMA_CHANNEL channel ) ;
10024 DMA_MODULE_ID index ,
10025 DMA_CHANNEL channel ) ;
10055 DMA_MODULE_ID index ,
10056 DMA_CHANNEL channel ) ;
10085 DMA_MODULE_ID index ,
10086 DMA_CHANNEL channel ) ;
10114 DMA_MODULE_ID index ,
10115 DMA_CHANNEL channel ) ;
10145 DMA_MODULE_ID index ,
10146 DMA_CHANNEL channel ) ;
10173 DMA_MODULE_ID index ,
10174 DMA_CHANNEL channel ) ;
10210 DMA_MODULE_ID index ,
10211 DMA_CHANNEL channel ) ;
10242 DMA_MODULE_ID index ,
10243 DMA_CHANNEL channel ) ;
10276 DMA_MODULE_ID index ) ;
10305 DMA_MODULE_ID index ) ;
10335 DMA_MODULE_ID index ) ;
10364 DMA_MODULE_ID index ) ;
10393 DMA_MODULE_ID index ) ;
10423 DMA_MODULE_ID index ) ;
10451 DMA_MODULE_ID index ) ;
10479 DMA_MODULE_ID index ) ;
10507 DMA_MODULE_ID index ) ;
10536 DMA_MODULE_ID index ) ;
10564 DMA_MODULE_ID index ) ;
10598 DMA_MODULE_ID index ) ;
10628 DMA_MODULE_ID index ) ;
10658 DMA_MODULE_ID index ) ;
10687 DMA_MODULE_ID index ) ;
10722 DMA_MODULE_ID index ,
10723 DMA_CHANNEL channel ) ;
10752 DMA_MODULE_ID index ) ;
10784 DMA_MODULE_ID index ,
10785 DMA_CRC_TYPE CRCType ) ;
10816 DMA_MODULE_ID index ) ;
10846 DMA_MODULE_ID index ) ;
10876 DMA_MODULE_ID index ) ;
10906 DMA_MODULE_ID index ) ;
10935 DMA_MODULE_ID index ) ;
10965 DMA_MODULE_ID index ) ;
10994 DMA_MODULE_ID index ) ;
11024 DMA_MODULE_ID index ,
11025 uint8_t polyLength ) ;
11054 DMA_MODULE_ID index ) ;
11083 DMA_MODULE_ID index ,
11084 DMA_CRC_BIT_ORDER bitOrder ) ;
11115 DMA_MODULE_ID index ) ;
11144 DMA_MODULE_ID index ) ;
11174 DMA_MODULE_ID index ,
11175 DMA_CRC_BYTE_ORDER byteOrder ) ;
11204 DMA_MODULE_ID index ) ;
11235 DMA_MODULE_ID index ) ;
11267 DMA_MODULE_ID index ,
11268 uint32_t DMACRCdata ) ;
11299 DMA_MODULE_ID index ) ;
11332 DMA_MODULE_ID index ,
11333 uint32_t DMACRCXOREnableMask ) ;
11371 DMA_MODULE_ID index ,
11372 DMA_CHANNEL dmaChannel ) ;
11409 DMA_MODULE_ID index ,
11410 DMA_CHANNEL dmaChannel ,
11411 uint32_t sourceStartAddress ) ;
11445 DMA_MODULE_ID index ,
11446 DMA_CHANNEL dmaChannel ) ;
11484 DMA_MODULE_ID index ,
11485 DMA_CHANNEL dmaChannel ,
11486 uint32_t destinationStartAddress ) ;
11526 DMA_MODULE_ID index ,
11527 DMA_CHANNEL dmaChannel ) ;
11566 DMA_MODULE_ID index ,
11567 DMA_CHANNEL dmaChannel ,
11568 uint16_t sourceSize ) ;
11603 DMA_MODULE_ID index ,
11604 DMA_CHANNEL dmaChannel ) ;
11641 DMA_MODULE_ID index ,
11642 DMA_CHANNEL dmaChannel ,
11643 uint16_t destinationSize ) ;
11677 DMA_MODULE_ID index ,
11678 DMA_CHANNEL dmaChannel ) ;
11713 DMA_MODULE_ID index ,
11714 DMA_CHANNEL dmaChannel ) ;
11749 DMA_MODULE_ID index ,
11750 DMA_CHANNEL dmaChannel ) ;
11787 DMA_MODULE_ID index ,
11788 DMA_CHANNEL dmaChannel ,
11789 uint16_t CellSize ) ;
11823 DMA_MODULE_ID index ,
11824 DMA_CHANNEL dmaChannel ) ;
11861 DMA_MODULE_ID index ,
11862 DMA_CHANNEL dmaChannel ) ;
11901 DMA_MODULE_ID index ,
11902 DMA_CHANNEL dmaChannel ,
11903 uint16_t patternData ) ;
11947 DMA_MODULE_ID index ,
11948 DMA_CHANNEL dmaChannel ,
11949 DMA_INT_TYPE dmaINTSource ) ;
11984 DMA_MODULE_ID index ,
11985 DMA_CHANNEL dmaChannel ,
11986 DMA_INT_TYPE dmaINTSource ) ;
12022 DMA_MODULE_ID index ,
12023 DMA_CHANNEL dmaChannel ,
12024 DMA_INT_TYPE dmaINTSource ) ;
12058 DMA_MODULE_ID index ,
12059 DMA_CHANNEL dmaChannel ,
12060 DMA_INT_TYPE dmaINTSource ) ;
12094 DMA_MODULE_ID index ,
12095 DMA_CHANNEL dmaChannel ,
12096 DMA_INT_TYPE dmaINTSource ) ;
12134 DMA_MODULE_ID index ,
12135 DMA_CHANNEL dmaChannel ,
12136 DMA_INT_TYPE dmaINTSource ) ;
12169 DMA_MODULE_ID index ,
12170 DMA_CHANNEL dmaChannel ,
12171 DMA_PATTERN_LENGTH patternLen ) ;
12204 DMA_MODULE_ID index ,
12205 DMA_CHANNEL dmaChannel ) ;
12235 DMA_MODULE_ID index ,
12236 DMA_CHANNEL channel ) ;
12269 DMA_MODULE_ID index ,
12270 DMA_CHANNEL channel ) ;
12300 DMA_MODULE_ID index ,
12301 DMA_CHANNEL channel ) ;
12333 DMA_MODULE_ID index ,
12334 DMA_CHANNEL channel ,
12335 uint8_t pattern ) ;
12366 DMA_MODULE_ID index ,
12367 DMA_CHANNEL channel ) ;
12399 DMA_MODULE_ID index ) ;
12424 DMA_MODULE_ID index ) ;
12448 DMA_MODULE_ID index ) ;
12473 DMA_MODULE_ID index ) ;
12496 DMA_MODULE_ID index ) ;
12520 DMA_MODULE_ID index ) ;
12543 DMA_MODULE_ID index ) ;
12567 DMA_MODULE_ID index ) ;
12591 DMA_MODULE_ID index ) ;
12616 DMA_MODULE_ID index ) ;
12640 DMA_MODULE_ID index ) ;
12664 DMA_MODULE_ID index ) ;
12687 DMA_MODULE_ID index ) ;
12711 DMA_MODULE_ID index ) ;
12735 DMA_MODULE_ID index ) ;
12759 DMA_MODULE_ID index ) ;
12783 DMA_MODULE_ID index ) ;
12807 DMA_MODULE_ID index ) ;
12830 DMA_MODULE_ID index ) ;
12855 DMA_MODULE_ID index ) ;
12880 DMA_MODULE_ID index ) ;
12904 DMA_MODULE_ID index ) ;
12929 DMA_MODULE_ID index ) ;
12953 DMA_MODULE_ID index ) ;
12977 DMA_MODULE_ID index ) ;
13003 DMA_MODULE_ID index ) ;
13028 DMA_MODULE_ID index ) ;
13052 DMA_MODULE_ID index ) ;
13077 DMA_MODULE_ID index ) ;
13100 DMA_MODULE_ID index ) ;
13123 DMA_MODULE_ID index ) ;
13146 DMA_MODULE_ID index ) ;
13169 DMA_MODULE_ID index ) ;
13194 DMA_MODULE_ID index ) ;
13219 DMA_MODULE_ID index ) ;
13243 DMA_MODULE_ID index ) ;
13268 DMA_MODULE_ID index ) ;
13292 DMA_MODULE_ID index ) ;
13316 DMA_MODULE_ID index ) ;
13339 DMA_MODULE_ID index ) ;
13362 DMA_MODULE_ID index ) ;
13386 DMA_MODULE_ID index ) ;
13410 DMA_MODULE_ID index ) ;
13434 DMA_MODULE_ID index ) ;
13461 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13474 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13487 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13517 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13691 DMA_CRC_TYPE type ;
13697 uint8_t polyLength ;
13700 DMA_CRC_BIT_ORDER bitOrder ;
13703 DMA_CRC_BYTE_ORDER byteOrder ;
13713 uint32_t xorBitMask ;
13838 SYS_MODULE_OBJ
object ,
13839 DMA_CHANNEL activeChannel ) ;
13842 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13887 uintptr_t contextHandle ) ;
13933 const SYS_MODULE_INIT *
const init ) ;
13984 DMA_CHANNEL channel ) ;
14070 DMA_TRIGGER_SOURCE eventSrc ) ;
14148 DMA_PATTERN_LENGTH length ,
14150 uint8_t ignorePattern ) ;
14403 const void * srcAddr ,
14405 const void * destAddr ,
14407 size_t cellSize ) ;
14504 const void * srcAddr ,
14506 const void * destAddr ,
14508 size_t cellSize ) ;
14704 const uintptr_t contextHandle ) ;
15000 DMA_TRIGGER_SOURCE eventSrc ) ;
15179 SYS_MODULE_OBJ
object ,
15180 DMA_CHANNEL activeChannel ) ;
15190 SYS_MODULE_OBJ
object ) ;
15200 SYS_MODULE_OBJ
object ,
15201 DMA_CHANNEL activeChannel ) ;
15228 #define DRV_USART_INDEX_0 0 15229 #define DRV_USART_INDEX_1 1 15230 #define DRV_USART_INDEX_2 2 15231 #define DRV_USART_INDEX_3 3 15232 #define DRV_USART_INDEX_4 4 15233 #define DRV_USART_INDEX_5 5 15247 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 15258 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 15269 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 15303 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15454 uintptr_t context ) ;
15502 USART_HANDSHAKE_MODE_FLOW_CONTROL
15506 USART_HANDSHAKE_MODE_SIMPLEX
15668 } AddressedModeInit ;
15693 = USART_ERROR_PARITY
15698 = USART_ERROR_FRAMING
15703 = USART_ERROR_RECEIVER_OVERRUN
15785 SYS_MODULE_INIT moduleInit ;
15789 USART_MODULE_ID usartID ;
15807 uint32_t brgClock ;
15823 USART_OPERATION_MODE linesEnable ;
15827 INT_SOURCE interruptTransmit ;
15831 INT_SOURCE interruptReceive ;
15835 INT_SOURCE interruptError ;
15840 unsigned int queueSizeReceive ;
15845 unsigned int queueSizeTransmit ;
15849 DMA_CHANNEL dmaChannelTransmit ;
15853 DMA_CHANNEL dmaChannelReceive ;
15857 INT_SOURCE dmaInterruptTransmit ;
15861 INT_SOURCE dmaInterruptReceive ;
15945 const SYS_MODULE_INDEX index ,
15946 const SYS_MODULE_INIT *
const init ) ;
15984 SYS_MODULE_OBJ
object ) ;
16022 SYS_MODULE_OBJ
object ) ;
16063 SYS_MODULE_OBJ
object ) ;
16104 SYS_MODULE_OBJ
object ) ;
16145 SYS_MODULE_OBJ
object ) ;
16224 const SYS_MODULE_INDEX index ,
16408 const size_t size ) ;
16601 const size_t size ) ;
16689 const uintptr_t context ) ;
16956 const size_t numbytes ) ;
17024 const size_t numbytes ) ;
17161 const uint8_t byte ) ;
17379 const SYS_MODULE_INDEX index ,
17432 const SYS_MODULE_INDEX index ,
17481 const SYS_MODULE_INDEX index ,
17696 #ifndef _DRV_USART_FEATURE_MAPPING_H 17697 #define _DRV_USART_FEATURE_MAPPING_H 17706 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17707 #define _DRV_USART_InterruptSourceEnable( source ) 17708 #define _DRV_USART_InterruptSourceDisable( source ) false 17709 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17710 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17711 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17712 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17713 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17716 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17725 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17726 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17727 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17728 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17729 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17742 #include "system/clk/sys_clk.h" 17743 #include "system/int/sys_int.h" 17781 #ifndef _SYS_DEBUG_H 17782 #define _SYS_DEBUG_H 17783 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17786 #define SYS_DEBUG_BUFFER_DMA_READY 17836 #define SYS_DEBUG_INDEX_0 0 17852 SYS_MODULE_INIT moduleInit ;
17856 SYS_MODULE_INDEX consoleIndex ;
17904 const SYS_MODULE_INDEX index ,
17905 const SYS_MODULE_INIT *
const init ) ;
17945 SYS_MODULE_OBJ
object ,
17946 const SYS_MODULE_INIT *
const init ) ;
17976 SYS_MODULE_OBJ
object ) ;
18009 SYS_MODULE_OBJ
object ) ;
18053 SYS_MODULE_OBJ
object ) ;
18096 const char * message ) ;
18146 const char * format ,
18236 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 18280 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 18323 #define SYS_MESSAGE( message ) 18356 #define SYS_DEBUG_MESSAGE( level , message ) 18403 #define SYS_PRINT( fmt ,... ) 18451 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18476 #define SYS_DEBUG_BreakPoint( ) 18485 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18486 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18487 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18504 #define _DRV_USART_RX_DEPTH 9 18570 const SYS_MODULE_INDEX index ,
18595 const uint8_t byte ) ;
18666 #ifndef _SYS_PORTS_H 18667 #define _SYS_PORTS_H 18706 #ifndef _SYS_PORTS_DEFINITIONS_H 18707 #define _SYS_PORTS_DEFINITIONS_H 18713 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18714 #include "system/common/sys_common.h" 18715 #include "system/common/sys_module.h" 18752 #ifndef _PLIB_PORTS_H 18753 #define _PLIB_PORTS_H 18754 #include <stdint.h> 18755 #include <stddef.h> 18820 #ifndef _PLIB_PORTS_PROCESSOR_H 18821 #define _PLIB_PORTS_PROCESSOR_H 18822 #error "Can't find header" 18872 PORTS_MODULE_ID index ,
18873 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18874 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18917 PORTS_MODULE_ID index ,
18918 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18919 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18954 PORTS_MODULE_ID index ,
18955 PORTS_ANALOG_PIN pin ,
18956 PORTS_PIN_MODE mode ) ;
18996 PORTS_MODULE_ID index ,
18997 PORTS_CHANNEL channel ,
18998 PORTS_BIT_POS bitPos ,
18999 PORTS_PIN_MODE mode ) ;
19034 PORTS_MODULE_ID index ,
19035 PORTS_CHANNEL channel ,
19036 PORTS_BIT_POS bitPos ) ;
19070 PORTS_MODULE_ID index ,
19071 PORTS_CHANNEL channel ,
19072 PORTS_BIT_POS bitPos ) ;
19109 PORTS_MODULE_ID index ,
19110 PORTS_CHANNEL channel ,
19111 PORTS_BIT_POS bitPos ) ;
19152 PORTS_MODULE_ID index ,
19153 PORTS_CHANNEL channel ,
19154 PORTS_BIT_POS bitPos ) ;
19193 PORTS_MODULE_ID index ,
19194 PORTS_CHANNEL channel ,
19195 PORTS_BIT_POS bitPos ) ;
19233 PORTS_MODULE_ID index ,
19234 PORTS_CHANNEL channel ,
19235 PORTS_BIT_POS bitPos ) ;
19270 PORTS_MODULE_ID index ,
19271 PORTS_CHANNEL channel ) ;
19306 PORTS_MODULE_ID index ,
19307 PORTS_CHANNEL channel ) ;
19344 PORTS_MODULE_ID index ,
19345 PORTS_CHANNEL channel ) ;
19382 PORTS_MODULE_ID index ,
19383 PORTS_CHANNEL channel ) ;
19420 PORTS_MODULE_ID index ,
19421 PORTS_CHANNEL channel ,
19422 PORTS_BIT_POS bitPos ) ;
19459 PORTS_MODULE_ID index ,
19460 PORTS_CHANNEL channel ,
19461 PORTS_BIT_POS bitPos ) ;
19499 PORTS_MODULE_ID index ,
19500 PORTS_CHANNEL channel ,
19501 PORTS_BIT_POS bitPos ) ;
19538 PORTS_MODULE_ID index ,
19539 PORTS_CHANNEL channel ,
19540 PORTS_BIT_POS bitPos ,
19575 PORTS_MODULE_ID index ,
19576 PORTS_CHANNEL channel ,
19577 PORTS_BIT_POS bitPos ) ;
19611 PORTS_MODULE_ID index ,
19612 PORTS_CHANNEL channel ,
19613 PORTS_BIT_POS bitPos ) ;
19647 PORTS_MODULE_ID index ,
19648 PORTS_CHANNEL channel ,
19649 PORTS_BIT_POS bitPos ) ;
19684 PORTS_MODULE_ID index ,
19685 PORTS_CHANNEL channel ,
19686 PORTS_BIT_POS bitPos ) ;
19721 PORTS_MODULE_ID index ,
19722 PORTS_CHANNEL channel ,
19723 PORTS_BIT_POS bitPos ) ;
19757 PORTS_MODULE_ID index ,
19758 PORTS_CHANNEL channel ,
19759 PORTS_BIT_POS bitPos ) ;
19793 PORTS_MODULE_ID index ,
19794 PORTS_CHANNEL channel ,
19795 PORTS_BIT_POS bitPos ) ;
19833 PORTS_MODULE_ID index ,
19834 PORTS_CHANNEL channel ) ;
19868 PORTS_MODULE_ID index ,
19869 PORTS_CHANNEL channel ) ;
19903 PORTS_MODULE_ID index ,
19904 PORTS_CHANNEL channel ,
19947 PORTS_MODULE_ID index ,
19948 PORTS_CHANNEL channel ,
19984 PORTS_MODULE_ID index ,
19985 PORTS_CHANNEL channel ,
20020 PORTS_MODULE_ID index ,
20021 PORTS_CHANNEL channel ,
20057 PORTS_MODULE_ID index ,
20058 PORTS_CHANNEL channel ,
20093 PORTS_MODULE_ID index ,
20094 PORTS_CHANNEL channel ,
20127 PORTS_MODULE_ID index ,
20128 PORTS_CHANNEL channel ) ;
20162 PORTS_MODULE_ID index ,
20163 PORTS_CHANNEL channel ,
20199 PORTS_MODULE_ID index ,
20200 PORTS_CHANNEL channel ,
20246 PORTS_MODULE_ID index ,
20247 PORTS_CHANNEL channel ,
20249 PORTS_PIN_MODE mode ) ;
20291 PORTS_MODULE_ID index ,
20292 PORTS_CHANNEL channel ,
20335 PORTS_MODULE_ID index ,
20336 PORTS_CHANNEL channel ,
20376 PORTS_MODULE_ID index ,
20377 PORTS_CHANNEL channel ,
20417 PORTS_MODULE_ID index ,
20418 PORTS_CHANNEL channel ,
20462 PORTS_MODULE_ID index ,
20463 PORTS_CHANNEL channel ,
20507 PORTS_MODULE_ID index ,
20508 PORTS_CHANNEL channel ,
20554 PORTS_MODULE_ID index ,
20555 PORTS_AN_PIN anPins ,
20556 PORTS_PIN_MODE mode ) ;
20599 PORTS_MODULE_ID index ,
20600 PORTS_CN_PIN cnPins ) ;
20644 PORTS_MODULE_ID index ,
20645 PORTS_CN_PIN cnPins ) ;
20688 PORTS_MODULE_ID index ,
20689 PORTS_CN_PIN cnPins ) ;
20732 PORTS_MODULE_ID index ,
20733 PORTS_CN_PIN cnPins ) ;
20767 PORTS_MODULE_ID index ) ;
20800 PORTS_MODULE_ID index ) ;
20836 PORTS_MODULE_ID index ,
20837 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20873 PORTS_MODULE_ID index ,
20874 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20911 PORTS_MODULE_ID index ) ;
20945 PORTS_MODULE_ID index ) ;
20981 PORTS_MODULE_ID index ,
20982 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
21018 PORTS_MODULE_ID index ,
21019 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
21064 PORTS_MODULE_ID index ,
21065 PORTS_CHANNEL channel ,
21067 PORTS_PIN_SLEW_RATE slewRate ) ;
21104 PORTS_PIN_SLEW_RATE
21106 PORTS_MODULE_ID index ,
21107 PORTS_CHANNEL channel ,
21108 PORTS_BIT_POS bitPos ) ;
21147 PORTS_MODULE_ID index ,
21148 PORTS_CHANNEL channel ,
21149 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
21182 PORTS_CHANGE_NOTICE_METHOD
21184 PORTS_MODULE_ID index ,
21185 PORTS_CHANNEL channel ) ;
21233 PORTS_MODULE_ID index ,
21234 PORTS_CHANNEL channel ,
21284 PORTS_MODULE_ID index ,
21285 PORTS_CHANNEL channel ,
21333 PORTS_MODULE_ID index ,
21334 PORTS_CHANNEL channel ,
21335 PORTS_BIT_POS bitPos ,
21336 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21379 PORTS_MODULE_ID index ,
21380 PORTS_CHANNEL channel ,
21381 PORTS_BIT_POS bitPos ) ;
21412 PORTS_MODULE_ID index ) ;
21436 PORTS_MODULE_ID index ) ;
21460 PORTS_MODULE_ID index ) ;
21484 PORTS_MODULE_ID index ) ;
21509 PORTS_MODULE_ID index ) ;
21534 PORTS_MODULE_ID index ) ;
21565 PORTS_MODULE_ID index ) ;
21593 PORTS_MODULE_ID index ) ;
21620 PORTS_MODULE_ID index ) ;
21645 PORTS_MODULE_ID index ) ;
21672 PORTS_MODULE_ID index ) ;
21697 PORTS_MODULE_ID index ) ;
21724 PORTS_MODULE_ID index ) ;
21749 PORTS_MODULE_ID index ) ;
21777 PORTS_MODULE_ID index ) ;
21805 PORTS_MODULE_ID index ) ;
21833 PORTS_MODULE_ID index ) ;
21859 PORTS_MODULE_ID index ) ;
21885 PORTS_MODULE_ID index ) ;
21911 PORTS_MODULE_ID index ) ;
21936 PORTS_MODULE_ID index ) ;
21962 PORTS_MODULE_ID index ) ;
21989 PORTS_MODULE_ID index ) ;
22014 PORTS_MODULE_ID index ) ;
22049 #ifndef _PLIB_PORTS_COMPATIBILITY_H 22050 #define _PLIB_PORTS_COMPATIBILITY_H 22051 #include <stdint.h> 22052 #include <stddef.h> 22087 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 22104 #include "system/int/sys_int.h" 22238 PORTS_MODULE_ID index ,
22239 PORTS_CHANNEL channel ) ;
22271 PORTS_MODULE_ID index ,
22272 PORTS_CHANNEL channel ,
22302 PORTS_MODULE_ID index ,
22303 PORTS_CHANNEL channel ) ;
22341 PORTS_MODULE_ID index ,
22342 PORTS_CHANNEL channel ,
22376 PORTS_MODULE_ID index ,
22377 PORTS_CHANNEL channel ,
22414 PORTS_MODULE_ID index ,
22416 PORTS_CHANNEL channel ,
22446 PORTS_MODULE_ID index ,
22447 PORTS_CHANNEL channel ) ;
22478 PORTS_MODULE_ID index ,
22479 PORTS_CHANNEL channel ,
22511 PORTS_MODULE_ID index ,
22512 PORTS_CHANNEL channel ,
22544 PORTS_MODULE_ID index ,
22545 PORTS_CHANNEL channel ,
22579 PORTS_MODULE_ID index ,
22580 PORTS_CHANNEL channel ) ;
22620 PORTS_MODULE_ID index ,
22621 PORTS_REMAP_INPUT_FUNCTION
function ,
22622 PORTS_REMAP_INPUT_PIN remapPin ) ;
22657 PORTS_MODULE_ID index ,
22658 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22659 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22692 PORTS_MODULE_ID index ) ;
22720 PORTS_MODULE_ID index ) ;
22754 PORTS_MODULE_ID index ,
22755 PORTS_CHANGE_NOTICE_PIN pinNum ,
22787 PORTS_MODULE_ID index ,
22788 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22817 PORTS_MODULE_ID index ) ;
22846 PORTS_MODULE_ID index ) ;
22877 PORTS_MODULE_ID index ,
22878 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22909 PORTS_MODULE_ID index ,
22910 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22949 PORTS_MODULE_ID index ,
22950 PORTS_ANALOG_PIN pin ,
22951 PORTS_PIN_MODE mode ) ;
22988 PORTS_MODULE_ID index ,
22989 PORTS_CHANNEL channel ,
22990 PORTS_BIT_POS bitPos ,
23025 PORTS_MODULE_ID index ,
23026 PORTS_CHANNEL channel ,
23027 PORTS_BIT_POS bitPos ) ;
23060 PORTS_MODULE_ID index ,
23061 PORTS_CHANNEL channel ,
23062 PORTS_BIT_POS bitPos ) ;
23095 PORTS_MODULE_ID index ,
23096 PORTS_CHANNEL channel ,
23097 PORTS_BIT_POS bitPos ) ;
23130 PORTS_MODULE_ID index ,
23131 PORTS_CHANNEL channel ,
23132 PORTS_BIT_POS bitPos ) ;
23165 PORTS_MODULE_ID index ,
23166 PORTS_CHANNEL channel ,
23167 PORTS_BIT_POS bitPos ) ;
23204 PORTS_MODULE_ID index ,
23206 PORTS_CHANNEL channel ,
23207 PORTS_BIT_POS bitPos ) ;
23240 PORTS_MODULE_ID index ,
23241 PORTS_CHANNEL channel ,
23242 PORTS_BIT_POS bitPos ) ;
23275 PORTS_MODULE_ID index ,
23276 PORTS_CHANNEL channel ,
23277 PORTS_BIT_POS bitPos ) ;
23310 PORTS_MODULE_ID index ,
23311 PORTS_CHANNEL channel ,
23312 PORTS_BIT_POS bitPos ) ;
23345 PORTS_MODULE_ID index ,
23346 PORTS_CHANNEL channel ,
23347 PORTS_BIT_POS bitPos ) ;
23380 PORTS_MODULE_ID index ,
23381 PORTS_CHANNEL channel ,
23382 PORTS_BIT_POS bitPos ) ;
23415 PORTS_MODULE_ID index ,
23416 PORTS_CHANNEL channel ,
23417 PORTS_BIT_POS bitPos ) ;
23450 PORTS_MODULE_ID index ,
23451 PORTS_CHANNEL channel ,
23452 PORTS_BIT_POS bitPos ,
23535 #ifndef _DRV_SPI_DEFINITIONS_H 23536 #define _DRV_SPI_DEFINITIONS_H 23542 #include <stdint.h> 23543 #include <stdbool.h> 23544 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23545 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23581 #ifndef _PLIB_SPI_H 23582 #define _PLIB_SPI_H 23616 #ifndef _PLIB_SPI_PROCESSOR_H 23617 #define _PLIB_SPI_PROCESSOR_H 23618 #error "Can't find header" 23663 SPI_MODULE_ID index ) ;
23693 SPI_MODULE_ID index ) ;
23725 SPI_MODULE_ID index ) ;
23757 SPI_MODULE_ID index ) ;
23791 SPI_MODULE_ID index ) ;
23821 SPI_MODULE_ID index ) ;
23858 SPI_MODULE_ID index ) ;
23897 SPI_MODULE_ID index ) ;
23927 SPI_MODULE_ID index ,
23958 SPI_MODULE_ID index ,
23992 SPI_MODULE_ID index ,
23993 SPI_COMMUNICATION_WIDTH width ) ;
24028 SPI_MODULE_ID index ,
24029 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
24061 SPI_MODULE_ID index ,
24062 SPI_INPUT_SAMPLING_PHASE phase ) ;
24094 SPI_MODULE_ID index ,
24095 SPI_OUTPUT_DATA_PHASE phase ) ;
24126 SPI_MODULE_ID index ,
24127 SPI_CLOCK_POLARITY polarity ) ;
24157 SPI_MODULE_ID index ) ;
24187 SPI_MODULE_ID index ) ;
24225 SPI_MODULE_ID index ,
24226 uint32_t clockFrequency ,
24227 uint32_t baudRate ) ;
24258 SPI_MODULE_ID index ) ;
24290 SPI_MODULE_ID index ) ;
24323 SPI_MODULE_ID index ) ;
24356 SPI_MODULE_ID index ) ;
24388 SPI_MODULE_ID index ) ;
24418 SPI_MODULE_ID index ) ;
24449 SPI_MODULE_ID index ) ;
24480 SPI_MODULE_ID index ) ;
24511 SPI_MODULE_ID index ) ;
24543 SPI_MODULE_ID index ,
24544 SPI_FIFO_TYPE type ) ;
24576 SPI_MODULE_ID index ) ;
24608 SPI_MODULE_ID index ) ;
24642 SPI_MODULE_ID index ,
24643 SPI_FIFO_INTERRUPT mode ) ;
24673 SPI_MODULE_ID index ) ;
24703 SPI_MODULE_ID index ) ;
24735 SPI_MODULE_ID index ,
24736 SPI_FRAME_PULSE_DIRECTION direction ) ;
24769 SPI_MODULE_ID index ,
24770 SPI_FRAME_PULSE_POLARITY polarity ) ;
24803 SPI_MODULE_ID index ,
24804 SPI_FRAME_PULSE_EDGE edge ) ;
24837 SPI_MODULE_ID index ,
24838 SPI_FRAME_PULSE_WIDTH width ) ;
24872 SPI_MODULE_ID index ,
24873 SPI_FRAME_SYNC_PULSE pulse ) ;
24905 SPI_MODULE_ID index ) ;
24935 SPI_MODULE_ID index ) ;
24967 SPI_MODULE_ID index ) ;
24997 SPI_MODULE_ID index ) ;
25027 SPI_MODULE_ID index ) ;
25057 SPI_MODULE_ID index ) ;
25088 SPI_MODULE_ID index ,
25120 SPI_MODULE_ID index ,
25152 SPI_MODULE_ID index ,
25175 SPI_MODULE_ID index ) ;
25206 SPI_MODULE_ID index ,
25207 SPI_BAUD_RATE_CLOCK type ) ;
25239 SPI_MODULE_ID index ,
25240 SPI_ERROR_INTERRUPT error ) ;
25272 SPI_MODULE_ID index ,
25273 SPI_ERROR_INTERRUPT error ) ;
25304 SPI_MODULE_ID index ,
25305 SPI_AUDIO_ERROR error ) ;
25336 SPI_MODULE_ID index ,
25337 SPI_AUDIO_ERROR error ) ;
25367 SPI_MODULE_ID index ) ;
25397 SPI_MODULE_ID index ) ;
25429 SPI_MODULE_ID index ,
25430 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25462 SPI_MODULE_ID index ,
25463 SPI_AUDIO_PROTOCOL mode ) ;
25496 SPI_MODULE_ID index ) ;
25522 SPI_MODULE_ID index ) ;
25548 SPI_MODULE_ID index ) ;
25573 SPI_MODULE_ID index ) ;
25598 SPI_MODULE_ID index ) ;
25623 SPI_MODULE_ID index ) ;
25649 SPI_MODULE_ID index ) ;
25674 SPI_MODULE_ID index ) ;
25699 SPI_MODULE_ID index ) ;
25724 SPI_MODULE_ID index ) ;
25749 SPI_MODULE_ID index ) ;
25774 SPI_MODULE_ID index ) ;
25800 SPI_MODULE_ID index ) ;
25825 SPI_MODULE_ID index ) ;
25850 SPI_MODULE_ID index ) ;
25875 SPI_MODULE_ID index ) ;
25901 SPI_MODULE_ID index ) ;
25927 SPI_MODULE_ID index ) ;
25953 SPI_MODULE_ID index ) ;
25977 SPI_MODULE_ID index ) ;
26002 SPI_MODULE_ID index ) ;
26027 SPI_MODULE_ID index ) ;
26052 SPI_MODULE_ID index ) ;
26078 SPI_MODULE_ID index ) ;
26103 SPI_MODULE_ID index ) ;
26128 SPI_MODULE_ID index ) ;
26153 SPI_MODULE_ID index ) ;
26178 SPI_MODULE_ID index ) ;
26203 SPI_MODULE_ID index ) ;
26229 SPI_MODULE_ID index ) ;
26256 SPI_MODULE_ID index ) ;
26281 SPI_MODULE_ID index ) ;
26307 SPI_MODULE_ID index ) ;
26333 SPI_MODULE_ID index ) ;
26359 SPI_MODULE_ID index ) ;
26384 SPI_MODULE_ID index ) ;
26409 SPI_MODULE_ID index ) ;
26435 SPI_MODULE_ID index ) ;
26461 SPI_MODULE_ID index ) ;
26473 #include "system/common/sys_common.h" 26474 #include "system/common/sys_module.h" 26475 #include "system/int/sys_int.h" 26476 #include "system/clk/sys_clk.h" 26477 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26515 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26527 #define DRV_SPI_INDEX_0 0 26528 #define DRV_SPI_INDEX_1 1 26529 #define DRV_SPI_INDEX_2 2 26530 #define DRV_SPI_INDEX_3 3 26531 #define DRV_SPI_INDEX_4 4 26532 #define DRV_SPI_INDEX_5 5 26544 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26793 SPI_MODULE_ID
spiId ;
26826 CLK_BUSES_PERIPHERAL
spiClk ;
26986 const SYS_MODULE_INDEX index ,
26987 const SYS_MODULE_INIT *
const init ) ;
27029 SYS_MODULE_OBJ
object ) ;
27078 SYS_MODULE_OBJ
object ) ;
27119 SYS_MODULE_OBJ
object ) ;
27184 const SYS_MODULE_INDEX drvIndex ,
27779 #include "driver/usb/usbhs/drv_usbhs.h" 27780 #include "usb/usb_device.h" 27808 #include <stdint.h> 27828 uint8_t RevNumber ;
27915 SYS_MODULE_OBJ sysTmr ;
27916 SYS_MODULE_OBJ drvTmr0 ;
27917 SYS_MODULE_OBJ drvTmr1 ;
27918 SYS_MODULE_OBJ drvTmr2 ;
27919 SYS_MODULE_OBJ drvTmr3 ;
27920 SYS_MODULE_OBJ drvTmr4 ;
27921 SYS_MODULE_OBJ drvUsart0 ;
27922 SYS_MODULE_OBJ drvPMP0 ;
27924 SYS_MODULE_OBJ spiObjectIdx0 ;
27926 SYS_MODULE_OBJ spiObjectIdx1 ;
27928 SYS_MODULE_OBJ spiObjectIdx2 ;
27929 SYS_MODULE_OBJ drvUSBObject ;
27930 SYS_MODULE_OBJ usbDevObject0 ;
27999 bool spi_write_complete_flag ;
28000 bool spi_sent_flag ;
28001 uint16_t adj [ 1 ] ;
28004 bool new_cont_values_flag ;
28006 uint16_t cont_prev ;
28007 uint16_t cont_new ;
28011 uint16_t update_rate ;
28012 uint16_t rate_time ;
28013 uint16_t update_count ;
28017 uint16_t sensor_offset ;
28019 uint16_t sensor_constant ;
28020 uint16_t max_current ;
28021 uint16_t current_limit ;
28022 uint16_t upper_current_limit ;
28023 uint8_t over_current_count ;
28024 bool new_current_values_flag ;
28025 bool new_voltage_values_flag ;
28026 bool overcurrent_flag ;
28027 bool overvoltage_flag ;
28128 #include "../system_config.h" 28129 #include "../system_definitions.h" 28130 #include <stdbool.h> 28139 #define NEGATIVE_OFFSET 0x02U 28140 #define POS_HIGH_OFFSET 0x01U 28141 #define POS_LOW_OFFSET 0x03U 28142 #define DEFAULT_OFFSET 0x04U 28143 #define I_ARRAY_SIZE 50U 28190 uint16_t voltage_limit ;
28191 uint16_t upper_voltage_limit ;
28192 uint16_t volt_count ;
28194 uint16_t max_current ;
28195 uint16_t current_limit ;
28196 uint16_t upper_current_limit ;
28197 uint8_t over_current_count ;
28198 uint8_t array_sum_count ;
28199 uint8_t array_count ;
28201 int16_t i_array [ 50U ] ;
28203 bool new_current_values_flag ;
28204 bool new_voltage_values_flag ;
28205 bool overcurrent_flag ;
28206 bool overvoltage_flag ;
28207 uint16_t sensor_offset ;
28208 uint16_t sensor_constant ;
28209 bool sensor_offset_tick ;
28210 uint16_t v_array [ 50 ] ;
28211 uint16_t v_array_count ;
28217 uint8_t overvoltage_count ;
28348 #include <stdbool.h> 28349 #include <stdint.h> 28381 uint8_t bitposn ) ;
28407 uint8_t bitposn ) ;
28501 #include <stdbool.h> 28502 #include <stdint.h> 28543 uint8_t command [ 7 ] ;
28544 bool process_complete_flag ;
28545 bool b_command_complete_flag ;
28546 bool sw_status_bit_check ;
28757 #include "../system_config.h" 28758 #include "../system_definitions.h" 28801 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
28917 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 17)));
28944 int zzqqzs = ((int)(
bitmapstruct.element2 |= (1 << 20)));
28958 int zzqqzs = ((int)(
bitmapstruct.element2 |= (1 << 21)));
28999 int zzqqzs = ((int)(
bitmapstruct.element2 |= (1 << 30)));
29011 int zzqqzs = ((int)(
bitmapstruct.element2 |= (1 << 31)));
29052 int zzqqzs = ((int)(
bitmapstruct.element3 |= (1 << 8)));
29063 int zzqqzs = ((int)(
bitmapstruct.element3 |= (1 << 9)));
29104 int zzqqzs = ((int)(
bitmapstruct.element3 |= (1 << 18)));
29115 int zzqqzs = ((int)(
bitmapstruct.element3 |= (1 << 19)));
29181 int izzqqzz=((int)(
bitmapstruct.element3 |= (1 << 31)));
29192 int zzqqzs = ((int)(
bitmapstruct.element4 |= (1 << 0)));
29221 int zzqqzs = ((int)(
bitmapstruct.element4 |= (1 << 5)));
29250 int zzqqzs = ((int)(
bitmapstruct.element4 |= (1 << 10)));
29296 int izzqqzz=((int)(
bitmapstruct.element4 |= (1 << 16)));
29873 int izzqqzz=((int)(
bitmapstruct.element7 |= (1 << 26)));
29893 int QZZZ = ((int)(
bitmapstruct.element7 |= (1 << 29)));
29914 int QZZZ = ((int)(
bitmapstruct.element8 |= (1 << 2)));
29939 int QZZZ = ((int)(
bitmapstruct.element8 |= (1 << 7)));
29960 int QZZZ = ((int)(
bitmapstruct.element8 |= (1 << 12)));
29974 #define qqqbranches 272 29975 #define QQQMAXMCDCSIZE 2 29979 #define ldra_sscanf 29995 #undef qqnull_params 29996 #define qqnull_params void 29998 #define qqzzidfield 1 30004 #define QQQFIXEDSIZE 30024 qqcptr = qqscan_str;
30026 while (qqcptr[0] ==
' ')
30032 if (qqcptr[0] ==
'-')
30038 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
30040 qqvalue = 10 * qqvalue;
30041 qqvalue = qqvalue + (qqcptr[0] -
'0');
30044 qqvalue = qqisign * qqvalue;
30070 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
30071 ldra_port_write (&ldra_buffer[0]);
30079 ldra_port_write(s);
30087 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
30088 ldra_port_write (&ldra_buffer[0]);
30096 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
30097 ldra_port_write (&ldra_buffer[0]);
30105 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
30106 ldra_port_write (&ldra_buffer[0]);
30225 static int branches_printed = 0;
30229 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
30230 ldra_port_write (&ldra_buffer[0]);
30231 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
30232 ldra_port_write (&ldra_buffer[0]);
30234 branches_printed += 8;
30254 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 30255 #define LASTELEMENT 30256 #include "switches_57zbelem.def" bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
static void DRV_TMR4_Close(void)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
void DRV_TMR2_StopInIdleEnable(void)
void DRV_TMR3_PeriodValueSet(uint32_t value)
static int switches_57zscanf(char *qqscan_str)
void APP_Initialize(void)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
void DRV_TMR2_StopInIdleDisable(void)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
SPI_BAUD_RATE_CLOCK baudClockSource
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void Prepare_Return_A(uint8_t byte, uint16_t data2, uint16_t data1)
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
uint32_t DRV_TMR2_CounterValueGet(void)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR3_CounterValueSet(uint32_t value)
static int switches_57zqzqzq(int qqqi)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
void DRV_TMR0_Initialize(void)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
uint8_t DRV_USART0_ReadByte(void)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
void SYS_DEBUG_Print(const char *format,...)
static void DRV_TMR3_Open(void)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
static void Execute_System(void)
SYS_STATUS DRV_USART0_Status(void)
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR4_Initialize(void)
static void DRV_TMR2_Close(void)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
DRV_USART_LINE_CONTROL_SET_RESULT
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR0_CounterValueSet(uint32_t value)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
static void store_switches(void)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
static int qqqstructzzopen
void DRV_USART0_TasksError(void)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
uint8_t jobQueueReserveSize
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
static void qqqqinitialise(int ii)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
SYS_MODULE_INIT moduleInit
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR3_CounterClear(void)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
uint32_t DRV_IC0_Capture32BitDataRead(void)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
uint32_t DRV_TMR3_CounterValueGet(void)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
static int qqqisinitialised
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
bool DRV_IC0_BufferIsEmpty(void)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
bool DRV_TMR_Start(DRV_HANDLE handle)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
bool DRV_TMR1_Start(void)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void DRV_TMR1_StopInIdleDisable(void)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static int switches_57zqendz(int qqqi)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
static void DRV_TMR1_Open(void)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
uint32_t DRV_TMR3_PeriodValueGet(void)
INT_SOURCE txInterruptSource
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
static void DRV_TMR0_DeInitialize(void)
void DRV_PMP0_Initialize(void)
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
void SYS_DEBUG_Message(const char *message)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void DRV_TMR3_StopInIdleDisable(void)
void SYS_DMA_Suspend(void)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
void DRV_ADC_Initialize(void)
void DRV_IC_Stop(DRV_HANDLE handle)
DRV_USART_TRANSFER_STATUS
DRV_USART_BAUD_SET_RESULT
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_DIRECTION framePulseDirection
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
bool DRV_SPIn_ReceiverBufferIsFull(void)
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
static void qqqupload(qqnull_params)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
void DRV_USART_Close(const DRV_HANDLE handle)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
#define switches_57zzopen
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR0_Open(void)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
SPI_FRAME_PULSE_WIDTH framePulseWidth
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
static unsigned char qqqzzglobflag
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint32_t DRV_TMR1_CounterValueGet(void)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
static void DRV_TMR2_Open(void)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
static void DRV_TMR1_DeInitialize(void)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
uint32_t DRV_TMR1_PeriodValueGet(void)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
static SYS_STATUS DRV_TMR0_Status(void)
void(* ldra_void_function)()
void DRV_PMP0_Write(uint8_t data)
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR0_PeriodValueGet(void)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
bool DRV_USART0_TransmitBufferIsFull(void)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_TMR2_CounterClear(void)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
uint32_t DRV_TMR4_PeriodValueGet(void)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
DRV_SPI_BUFFER_TYPE bufferType
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
bool DRV_TMR4_Start(void)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
uint32_t SYS_DMA_ChannelCRCGet(void)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
static void DRV_TMR4_Open(void)
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
uint16_t DRV_IC0_Capture16BitDataRead(void)
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
SYS_DMA_CHANNEL_IGNORE_MATCH
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
static void DRV_TMR2_Tasks(void)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
static void execute_switches(void)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_TMR2_Initialize(void)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
bool DRV_TMR2_Start(void)
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
void qqqtotalupload(void)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
static void Execute_Protocol_A(void)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
void DRV_SPI_Close(DRV_HANDLE handle)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
SPI_FRAME_PULSE_EDGE framePulseEdge
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
void DRV_TMR_Stop(DRV_HANDLE handle)
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
static void Execute_Auto_Protocol_A(void)
static void DRV_TMR0_Tasks(void)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void DRV_TMR1_CounterValueSet(uint32_t value)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_USART0_TasksTransmit(void)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void DRV_TMR2_CounterValueSet(uint32_t value)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
static int qqqqbmselwidth
uintptr_t DRV_USART_BUFFER_HANDLE
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
struct _DRV_SPI_INIT DRV_SPI_INIT
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
ldra_void_function qqqaccumupload[QQQnumfil]
void DRV_TMR4_StopInIdleDisable(void)
static void read_switches(void)
void DRV_USART0_TasksReceive(void)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
static void DRV_TMR3_Close(void)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
CLK_BUSES_PERIPHERAL spiClk
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
DRV_USART_LINE_CONTROL_SET_RESULT
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
static void DRV_TMR0_Close(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
void PLIB_USART_Disable(USART_MODULE_ID index)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
SPI_COMMUNICATION_WIDTH commWidth
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool DRV_TMR3_Start(void)
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
uintptr_t DRV_SPI_BUFFER_HANDLE
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
#define DRV_IC_Open(drvIndex, intent)
bool SYS_DMA_IsBusy(void)
static int switches_57zqqzqz(qqnull_params)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
static SYS_STATUS DRV_TMR1_Status(void)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
void DRV_TMR0_CounterClear(void)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
void DRV_USART0_Deinitialize(void)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
#define DRV_IC_Close(handle)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR2_DeInitialize(void)
static void DRV_TMR3_Tasks(void)
uint8_t dump_fire_switch_S7
void PLIB_USART_Enable(USART_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
void DRV_TMR4_CounterClear(void)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
bool GetDepthStatus(void)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR2_PeriodValueGet(void)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
void Set_HVPS_Ramp_Rate(uint16_t value)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
SYS_DMA_CHANNEL_CHAIN_PRIO
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void DRV_TMR0_PeriodValueSet(uint32_t value)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
void DRV_TMR1_PeriodValueSet(uint32_t value)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
static void DRV_TMR1_Tasks(void)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
void DRV_PMP0_ModeConfig(void)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void Set_WL_SPS_CurrentLimit(uint16_t value)
uint8_t knob_switch_S3[5]
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
void DRV_USART0_Close(void)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
bool DRV_TMR0_Start(void)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
static void qqoutput0(FILEPOINT char *s)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
void DRV_ADC1_Close(void)
static void Execute_Protocol_B(void)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
uintptr_t DRV_SPI_BUFFER_HANDLE
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
void SYS_PORTS_Initialize()
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
SPI_AUDIO_PROTOCOL audioProtocolMode
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
static SWITCH_STATES SW_STATES
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
DRV_SPI_CLOCK_MODE clockMode
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
static void DRV_TMR4_DeInitialize(void)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
static void process_switches(void)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
static void qqqbitmapreset(qqnull_params)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
uintptr_t SYS_DMA_CHANNEL_HANDLE
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_IC0_Initialize(void)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
DRV_USART_TRANSFER_STATUS
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
static void DRV_TMR3_DeInitialize(void)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
void DRV_TMR3_StopInIdleEnable(void)
INT_SOURCE rxInterruptSource
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
void DRV_TMR_Close(DRV_HANDLE handle)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
void DRV_TMR0_StopInIdleEnable(void)
uint32_t DRV_TMR4_CounterValueGet(void)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
uint8_t fire_switch_S1[2]
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
void DRV_TMR1_Initialize(void)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
static void DRV_TMR1_Close(void)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
void DRV_TMR4_CounterValueSet(uint32_t value)
static void qqoutput2(FILEPOINT char *s, int i, int j)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
void DRV_TMR1_StopInIdleEnable(void)
INT_SOURCE errInterruptSource
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
void Set_Status(uint8_t bitposn)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
ldra_void_function qqqaccumreset[QQQnumfil]
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
static SYS_STATUS DRV_TMR4_Status(void)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
void DRV_TMR2_PeriodValueSet(uint32_t value)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
static SYS_STATUS DRV_TMR3_Status(void)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void DRV_TMR3_Initialize(void)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_ADC_DeInitialize(void)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
void DRV_TMR1_CounterClear(void)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
uint32_t DRV_TMR0_CounterValueGet(void)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
void SYS_DMA_Resume(void)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
bool Valid_Command(uchar8_t msg)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
static struct bitmapstruct_t bitmapstruct
DRV_SPI_TASK_MODE taskMode
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
void DRV_TMR4_PeriodValueSet(uint32_t value)
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
void DRV_TMR0_StopInIdleDisable(void)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
#define switches_57zqqzqz1
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
void DRV_ADC0_Close(void)
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
void Prepare_Return_B(uint8_t byt [])
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
SYS_ERROR_LEVEL gblErrLvl
static void qqoutput(FILEPOINT char *s, int i)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void DRV_TMR4_Tasks(void)
uintptr_t DRV_USART_BUFFER_HANDLE
void Clear_Status(uint8_t bitposn)
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
uintptr_t SYS_DMA_CHANNEL_HANDLE
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
SPI_FRAME_SYNC_PULSE frameSyncPulse
static SYS_STATUS DRV_TMR2_Status(void)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
uint8_t DRV_PMP0_Read(void)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
bool DRV_SPIn_TransmitterBufferIsFull(void)
void DRV_TMR4_StopInIdleEnable(void)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
void DRV_USART0_WriteByte(const uint8_t byte)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
void SET_WL_SPS_IOffset(uint8_t mode)